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HKU Researchers Break the Capacity Limit of Brain-Inspired Associative Memory

6 Sep 2026

Researchers in the Department of Electrical and Computer Engineering of the Faculty of Engineering and the Centre for Advanced Semiconductors and Integrated Circuits (CASIC) at the University of Hong Kong (HKU) have made a breakthrough in brain-inspired computing. In collaboration with Hewlett Packard Labs, the team have developed a memristor chip that overcomes a long-standing limit on the capacity of "associative memory", the brain-like ability to recall complete information from a partial cue, while keeping it reliable even when a large fraction of the hardware fails.

Associative memory is something the brain does effortlessly: a few notes bring a whole song to mind, and a glimpse of a face identifies a person. Unlike the RAM in a computer, which must be told exactly where information is stored, associative memory retrieves it by content — the very capability that pattern completion, error correction and recognition depend on.

Conventionally, the capacity of such systems has been capped by the size of the network: the more patterns they store, the more easily they confuse them, and storing more has meant building a bigger network. For the first time, the research led by Professor Can Li, Associate Director of CASIC, and PhD candidate Mr Chengping He have shown that a hardware-adaptive learning algorithm, which measures and compensates for each chip’s real device defects during training, combined with a multilayer network design, can break this capacity ceiling on real memristor hardware.

Professor Li explained, “Real hardware is never perfect, so instead of fighting its imperfections, we taught the system to embrace them. By co-designing the algorithm and the hardware, we can store far more memories and keep them reliable even when devices fail, exactly what is needed to bring brain-inspired computing into the real world.”

The experiment results indicated that the same system handled both binary and continuous-valued data while using up to 95% fewer devices. The chip retained roughly double the storage capacity of the previous state-of-the-art design. On structured, real-world data, its capacity grew faster than the size of the network itself — a “Superlinear” scaling that conventional single-layer designs cannot achieve.

Because the chip updates its entire network at once, exploiting the natural parallelism of the memristor crossbar, it also cut recall time by up to 99.7% and improved energy efficiency by up to 8.8 times compared with conventional approaches. The results were demonstrated not only in simulation but on a fully integrated chip built around 64×64 memristor arrays.

The advance points towards robust, low-power neuromorphic hardware for memory-centric artificial intelligence (AI). It is especially promising for intelligent edge devices, from sensors to wearables, that must operate reliably on tight power budgets, far from the data centre.

The research article “A hardware-adaptive learning algorithm for superlinear-capacity associative memory on memristor crossbars” was published in Nature Communications.

Link to the paper: https://www.nature.com/articles/s41467-026-69958-0

About Professor Can Li
Professor Can Li is an Associate Professor in the Department of Electrical and Computer Engineering of the Faculty of Engineering at HKU and serves as Associate Director of the Centre for Advanced Semiconductors and Integrated Circuits at The University of Hong Kong. He earned his BS and MS from Peking University and his PhD from the University of Massachusetts Amherst, and previously worked at Hewlett Packard Labs before joining HKU. His group develops brain-inspired, memristor- and new-material-based computing hardware to overcome the limits of von Neumann architectures and enable energy-efficient AI, with applications spanning large-scale AI, quantum-inspired optimisation, and real-time genomic analysis. This work is regularly published in venues including Nature Nanotechnology and other Nature-series journals and IEEE IEDM. He is a Clarivate Highly Cited Researcher (2025) and a recipient of the Croucher Tak Wah Mak Innovation Award and the NSFC Excellent Young Scientists Fund.

Media Enquiries
Faculty of Engineering, HKU
Ms Christina Chung (Tel: 3910 3324; Email: chungmc@hku.hk)
Ms Natalie Yuen (Tel: 3917 1924; Email: natyuen@hku.hk)

Figure 1：How associative memory works, and why memristor hardware suits it. (a) The brain recalls a whole memory from a partial cue, and a Hopfield neural network reproduces the same behavior, restoring a stored pattern from a corrupted input. (b) In a conventional von Neumann computer the processing unit, the control unit and the memory are separate, so data must shuttle between them, which costs time and energy. (c) A memristor crossbar performs the computation where the data already sits, using Ohm’s law and Kirchhoff’s circuit laws. (d) Previous approaches relied on offline training, a single layer and binary patterns, while the hardware-adaptive learning proposed in this work supports multilayer architectures, works with both binary and continuous patterns, and tolerates device defects.

Figure 2：The integrated memristor chip used in the experiments. (a) The measurement system, comprising the memristor chip, a power supply, a microcontroller and peripheral circuitry. (b) Layout of the chip, which holds three 64×64 memristor crossbar arrays alongside fully integrated peripheral circuits, including transimpedance amplifiers (TIAs), multiplexers (MUXs), analog-to-digital converters (ADCs) and drivers. The memristors were fabricated by back-end-of-line processing in an in-house cleanroom, on top of CMOS circuits made in a 180 nm technology. (c) Optical microscopy image of one of the 64×64 memristor crossbar arrays. (d) Current-voltage characteristics of a single device over 100 cycles, the dark line showing the average. (e) Devices programmed to different conductance states keep a linear current-voltage relation, which is what accurate analog computing needs. (f) Retention of 16 conductance levels spanning 0 to 150 µS, each measured across 256 devices, stable beyond 100,000 seconds.

Figure 3：Breaking the capacity limit with a multilayer network. (a) The conventional single-layer Hopfield network compared with the multilayer structure that hardware-adaptive learning makes trainable. (b, c) Conductance read back from the memristor chip for the first and the second layer of a two-layer system. (d) Corrupted input patterns, generated by flipping 10% of the pixels of the stored patterns, the patterns retrieved experimentally by the chip, and the original stored patterns. (e) Retrieval quality against the number of stored patterns, for multilayer networks with different numbers of hidden neurons and for the single-layer network. The multilayer network stays accurate well beyond the point where the single-layer network fails. (f) Capacity against the number of input neurons, with the single-layer and multilayer networks holding the same number of synapses. On structured data the capacity of the multilayer network grows faster than the network itself, a superlinear scaling that the single-layer design cannot reach. (g) Capacity against the number of hidden neurons, with the input fixed at 400 neurons. (h) Memristors needed to store a given number of patterns in a 400-neuron system, where the multilayer design uses up to 95% fewer devices.

Figure 4：Recalling continuous-valued, grayscale patterns. (a) A conventional Hopfield network accepts only binary patterns, whereas the multilayer associative memory trained by hardware-adaptive learning handles binary and continuous-valued patterns alike. (b) Experimental readout weights of the first and the second layer, each weight represented by the conductance difference of two adjacent memristors. (c) Input patterns corrupted by Gaussian noise of amplitude 0.6, the patterns retrieved by the chip, and the original stored patterns. (d) At noise levels of 0.4, 0.5 and 0.6 the multilayer memory still recovers the correct pattern, while the single-layer network barely works. (e) Retrieval quality against iteration number, converging within a single iteration. (f) Capacity against the number of input neurons for continuous patterns, the hidden neurons set to half the input count. (g) Capacity against the number of hidden neurons for continuous patterns, with 400 neurons in total.

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Figure 1：How associative memory works, and why memristor hardware suits it. (a) The brain recalls a whole memory from a partial cue, and a Hopfield neural network reproduces the same behavior, restoring a stored pattern from a corrupted input. (b) In a conventional von Neumann computer the processing unit, the control unit and the memory are separate, so data must shuttle between them, which costs time and energy. (c) A memristor crossbar performs the computation where the data already sits, using Ohm’s law and Kirchhoff’s circuit laws. (d) Previous approaches relied on offline training, a single layer and binary patterns, while the hardware-adaptive learning proposed in this work supports multilayer architectures, works with both binary and continuous patterns, and tolerates device defects.

HKU Researchers Break the Capacity Limit of Brain-Inspired Associative Memory

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